In the design and manufacture of semiconductor devices, design rules are developed to enable successful design-for-manufacture. The design rules provide guidelines for constraining a design envelope such that a device designed within the design envelope will have a high probability of being manufacturable. Traditionally, design rules are developed based on capabilities of the manufacturing process. Also, traditional design rules are developed to accommodate a general design style. The general design style allows for layout of semiconductor device features in a given chip layer in essentially any two-dimensional configuration. Thus, it should be appreciated that the design rules associated with the general design style are defined to represent manufacturing process capabilities associated with manufacturing an essentially open-ended spectrum of two-dimensional device features and interactions.
Because the design rules for the general design style need to cover the manufacturable corners of the design envelope, the design rules for the general design style can be complex and difficult to manage. Also, if design rules defined to cover the manufacturable corners of the design envelope are utilized in developing a design that does not approach the corners of the design envelope, the developed design can be overly conservative. The conservatism in the developed design can manifest as increased expense, increased complexity, inefficient use of chip area, inefficient consumption of power, etc.
As semiconductor device size decreases, the photolithography requirements associated with device manufacture become limiting such that the design rules associated with the manufacturing process are driven by the photolithography requirements. More specifically, modern semiconductor device sizes are smaller than the wavelength of light used to pattern the devices in the photolithography process. For example, 193 nanometers (nm) is a common wavelength of light used to pattern feature sizes of about 65 nm. Lithographic gap refers to the difference between the wavelength of light used to pattern a particular feature and the actual size of the particular feature. A number of difficulties arise when patterning devices that are smaller than the light wavelength. For example, forbidden feature pitches may exist, wherein light used to pattern adjacent features adversely interacts such that the patterned features are unacceptably defined.
It should be appreciated that lithographic gap difficulties are further compounded in the general design style, wherein optical effects associated with patterning two-dimensional features are unpredictable and often unacceptable. Techniques such as optical proximity correction and reticle enhancement technology, among others, have been developed in an attempt to compensate for the lithographic gap difficulties. However, these techniques are not always capable of fully compensating for adverse feature patterning artifacts. Additionally, implementation of these techniques can be quite expensive with respect to economics and time.
To accommodate the drive toward smaller semiconductor device sizes while maintaining manufacturability at the corners of the general design style envelope, modern design rules are becoming cumbersome, if not impossible, to communicate and implement. Additionally, techniques used to compensate for lithographic gap are becoming more complicated and expensive to implement. In view of the foregoing, the traditional semiconductor device design-for-manufacture paradigm needs to be reconsidered.